Power control in ICs is becoming an increasingly important part of processor hardware design, and ample reasons exist to believe that IC power control will become even more important in the future. However, several serious problems are associated with power control in ICs.
For example, controlling power delivered to different types of memory can be complex. A retention cell, for example, has a dedicated, low-power storage area (called a retention area) for storing information when not in active use and an externally accessible area for storing information when in active use. However, timing transitions between the retention area and the accessible area can be challenging. Aside from memory issues such as this, just applying power to various parts of an IC (called “power domains”) can itself be challenging.
What is needed in the art is method and device that is employable with retention cells that addresses at least some of the deficiencies of the prior art.